1. Field
This disclosure relates generally to data processing systems, and more specifically, to a data processor having multiple low power modes.
2. Related Art
Static leakage power has become a significant portion of the power consumption of very large scale system-on-a-chip (SoC) integrated circuits. Reducing leakage current is becoming an increasingly important factor in extending battery life of, for example, handheld devices.
Most circuits in handheld devices are typically off, for example, in an idle or deep sleep mode, for a significant portion of time, consuming only leakage power. As transistor leakage currents increase with finer geometry manufacturing processes, it becomes more difficult to meet chip leakage targets using traditional power reduction techniques.
There are several methods for reducing leakage currents of integrated circuits during a low power mode. One method involves providing a “virtual” ground terminal that can be at ground potential during a normal operating mode and then increased above ground during a low power operating mode to reduce the leakage current. However, a minimum data retention voltage must be maintained when reducing the power supply voltage to cache memories of the system to avoid corruption of stored data.